ASIC Design: Co designing for Peak Performance
A speaker discusses the complexity of A6 chip design requiring co-design across technology, package, and board levels, particularly for chiplet platforms. They describe partnerships with major EDA companies while exploring internal AI-driven solutions leveraging their knowledge base.
Summary
The presentation focuses on the challenges of designing A6 chips with high-speed IO, emphasizing that successful implementation requires comprehensive co-design across multiple domains including technology, packaging, and board-level integration. The speaker highlights that achieving necessary performance targets demands this integrated approach rather than isolated design efforts. The complexity escalates significantly when dealing with chiplet platforms and multi-chip modules, where co-design and verification processes become incredibly intricate. The organization maintains strong partnerships with the three leading EDA companies - Cadence, Synopsis, and Simmons - working closely with these industry leaders. However, they are also pursuing internal research directions to develop differentiated solutions that can leverage their proprietary knowledge base through AI technology. This internal development effort represents an active and strategic area of focus, with specific mention of implementation plans in Qatar.
Key Insights
- The speaker states that designing A6 with high-speed IO must be co-designed with technology, package, and board to achieve required performance
- The speaker explains that chiplet platforms with multi-chip modules make co-design and verification incredibly complex
- The organization works closely with all three EDA leaders - Cadence, Synopsis, and Simmons - maintaining great partnerships
- The company is actively looking at developing something differentiated internally that can tap into their knowledge base using AI technology
- The speaker describes AI-driven internal development as a very interesting and active area they want to pursue in Qatar
Topics
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