ALU, Datapath and Control Unit | Part 1
This lecture covers the internal components of a CPU, including the ALU, various special and general purpose registers, and how they are interconnected via internal and external buses. The instructor builds a hypothetical CPU model (loosely based on the 8085 microprocessor) to explain how instructions are fetched, decoded, and executed. Key concepts like micro-operations, Register Transfer Language (RTL), and the role of the Timing and Control Unit are also introduced.
Summary
The lecture begins by zooming into the CPU as a 'black box' to identify its internal components. The instructor starts with the ALU (Arithmetic Logic Unit), describing it as a collection of hardware that performs arithmetic and logical operations. The ALU requires two inputs, which come from two special-purpose registers: the Accumulator and the Data Register (also called Temporary Register). The ALU produces two outputs — the result (which typically goes into the Accumulator) and a status output that feeds into the Flag Register.
The instructor then distinguishes between General Purpose Registers (GPRs) and Special Purpose Registers (SPRs). GPRs (like R0, R1, R2... arranged in powers of two for easy addressing) are used for temporary data storage during computation. SPRs serve specific functions: the Accumulator holds ALU results, the Data Register holds the second ALU operand, the Stack Pointer tracks the top of the runtime stack, the Program Counter holds the address of the next instruction, the Instruction Register holds the currently fetched instruction, and the Flag Register (also called Status Register or PSW - Program Status Word) holds condition flags.
The Flag Register is explained in detail using the 8085 microprocessor as an example. Despite being 8 bits wide, it contains only 5 active flags: Carry (C), Parity (P), Auxiliary Carry (A), Zero (Z), and Sign (S), with 3 unused bits. Each flag is a single flip-flop (1-bit memory cell) that reflects the status of the last ALU operation.
The instructor then addresses how all these components are interconnected, using the analogy of a bus topology in computer networks. Rather than drawing direct wires between every component (which would create a tangled mess), an Internal Bus is used inside the CPU to allow data transfer between components in a shared, time-multiplexed manner. The Timing and Control Unit acts as the central coordinator ('papa ji'), generating control signals to ensure only one component drives the bus at a time, preventing data collisions.
Two more special registers are introduced for interfacing with memory: the MAR (Memory Address Register), which connects to the external Address Bus, and the MDR (Memory Data Register), which connects to the external Data Bus. The instruction fetch process is walked through step-by-step as an example of micro-operations: (1) transfer PC content to MAR, (2) read memory at address in MAR into MDR, (3) transfer MDR content to Instruction Register, and (4) increment the Program Counter. Each of these steps is a micro-operation, represented using RTL (Register Transfer Language).
Finally, the three external buses are summarized: the Address Bus (unidirectional, CPU to RAM/IO devices), the Data Bus (bidirectional, between CPU and RAM/IO devices), and the Control Bus (bidirectional as a whole, but individual lines are unidirectional — carrying signals like read/write commands from CPU and ready signals from RAM). The lecture concludes by noting that micro-operations are represented in RTL, and more details will follow in the next lecture.
Key Insights
- The instructor explains that the ALU produces two outputs, not one — the computation result (which typically goes to the Accumulator) and a status output that updates the Flag Register, which contains condition flags like Carry, Zero, Parity, Auxiliary Carry, and Sign.
- The instructor clarifies that the 8085's Flag Register is 8 bits wide but contains only 5 active flags (C, P, A, Z, S), with 3 bits left unused — meaning an 8-bit flag register does not imply 8 distinct flag types.
- The instructor describes the Timing and Control Unit as the central coordinator of the CPU, responsible for generating control signals to all components to ensure that only one register drives the internal bus at any given time, preventing data collisions.
- The instructor explains that fetching a single instruction requires four distinct micro-operations: transferring PC to MAR, reading memory at that address into MDR, loading MDR content into the Instruction Register, and incrementing the Program Counter — each represented in Register Transfer Language (RTL).
- The instructor distinguishes the three external buses: the Address Bus is unidirectional (CPU to memory/IO), the Data Bus is bidirectional, and the Control Bus is bidirectional as a whole but its individual lines are each unidirectional, carrying signals like read/write commands and ready acknowledgments.
Topics
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